1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a photomask used in fabrication of a mask read only memory (ROM) device.
2. Description of Related Art
A memory device is widely used in the information industry, and is particularly used in microprocessors and computers. In order to achieve a faster speed of information exchange with more tremendous quantity in a more convenient way, the information products need the properties of small dimensions and reduced weight. The properties are necessarily met by a memory with higher memory capacity and faster access speed. Currently, a mask ROM with embedded bit lines is a common memory structure because it can be fabricated with very high integration.
The fabrication of a memory device includes not only forming a memory cell and encoding but also forming bonding pads. The fabrication processes for encoding and forming bonding pads also include photomasks with proper patterns.
A phototmask typically includes a transparent substrate, such as glass or quartz, a chromium shielding layer to form a desired pattern and an anti-reflection layer, such as a titanium nitride layer. The desired pattern of the photomask is transferred onto a semiconductor substrate through a light source so that it has an intrinsic issue of a pattern resolution. Particularly, when device dimension goes down to 0.25 microns or smaller, the light interference effect is stronger, and the pattern resolution cannot be further enhanced. Another typical design of a photomask, called a phase shift mask, is therefore proposed to improve the pattern resolution. The phase shift mask still uses light to transfer the pattern but includes one phase shift layer which can shift the light wave phase by 180 degrees to cause a light amplitude subtraction at the interface. Thus, the pattern resolution is improved.
FIGS. 1A-1D are cross-sectional views schematically illustrating a conventional fabrication process to form a mask ROM with a conventional photomask. In FIG. 1A, a silicon substrate 101 includes a memory region 105 and a bonding pad region 103. At the memory region 105, several bit lines 107 and word lines 111 are formed. At the bonding pad region 103, a field oxide layer 109 is formed. At this stage, the word lines 111 and the field oxide layer 109 remain exposed. A silicon oxide layer 113 is formed over the substrate 101 to cover the word lines 111 and the field oxide layer 109. A barrier layer 115 is formed on the silicon oxide layer 113. Then, processes for encoding the ROM device with a desired code, such as an execution program code, are performed at the memory region 105. Bonding pads are formed at the bonding pad region 103. The program code usually is determined by users, who order the ROM device, so the program code may be different in each order. In order to reduce fabrication time, a pad pattern is formed beforehand at the bonding pad region, since it has more common property. The formation of the program code at the memory region can wait until an order from the user.
Continuing to FIG. 1A, a photoresist layer 117 is formed on the barrier layer 115. A photomask 102 with an opening pattern is used to pattern the photoresist layer 117 to form a pad opening pattern, which is used for a formation of bonding pads later. Using the photoresist layer 117 with the pad opening pattern, the barrier layer 115 including titanium nitride is patterned to form an opening 119, which exposes the silicon oxide layer 113. A top view of the photomask 102 is shown in FIG. 2A. The opening pattern of the photomask 102 includes openings 207. The photomask 102 shown in FIG. 1A is one of the openings 207 at one side. The purpose of the opening 119 is to allow a bonding pad to be firmly formed later at the opening 119. This is because the bonding pad usually is made of aluminum, which has poor adhesion capability with the titanium nitride of the barrier layer 115. If the bonding pad is directly formed on the barrier layer 115, it may be easily pulled apart, and lose its contact with the ROM device.
In FIG. 1B, the photoresist layer 117 is removed. An encoding process is performed. The encoding process includes depositing a photoresist layer 121 over the substrate 101 to cover the barrier layer 115 and the silicon oxide layer 113 at a portion within the opening 119. A photomask 104 with a desired pattern required by users is used to pattern the photoresist layer 121, and then code areas 123, 125 are formed by further patterning the barrier layer 115, using the photoresist layer 121. The code areas 123 and 125 expose a portion of the silicon oxide layer 113. A top view of the photomask 104 is schematically illustrated in FIG. 2B. In FIG. 2B, the photomask 104 includes an opening pattern, which further includes several openings 203. Each of the openings 203 forms a code area. In FIG. 1B, the two code areas 123 and 125 are shown.
In FIG. 1C, using the photoresist layer 121 as a mask, an ion implantation process 122 is performed to implant phosphorus ions into the substrate 101 to form channel regions 127 and 129, corresponding to the code areas 123 and 125. A desired code is formed.
In FIG. 1D, the photoresist layer 121 is removed, and a metal layer is deposited over the substrate 101. After photolithography and etching, the metal layer and the barrier layer 115 of FIG. 1B are patterned to form a metal line pattern 133 and a bonding pad pattern 131. A passivation layer 135 is formed over the substrate 101 to protect the ROM device from damage. The passivation layer 135 is patterned to form an opening 137 that exposes the bonding pad pattern 131 so as to allow the device to be coupled to a lead frame through a bonding wire during packaging the ROM device.
In the conventional fabrication process described above, after the opening 119 is formed, it usually waits for a certain time until the order is placed. During this period, the barrier layer 115 may be easily eroded by the residual etchant from the previous etching process. Moreover, the formation of the opening 119 and the code areas 123 and 125 is performed by two individual steps of photolithography and etching. The fabrication cost and the fabrication efficiency are still not the most economical.